Semiconductor foundries and standard cell library vendors are continuously improving the designs of standard cells and reusable components.
Modern design processes for integrated circuits make extensive use of modular components. Circuit designers produce design descriptions, typically at a register-transfer level (RTL). The RTL source description (e.g., Verilog code) is compiled into instances of “cells.”. The cells are basic building blocks of circuits, such as gates or memory bit cells. Cells implement logic or other electronic functions. Various foundries and independent cell library vendors provide standard cell libraries. The cells in these libraries have been modeled and qualified, for use with a particular integrated circuit technology. Electronic Design Automation (EDA) tools place the selected standard cells at appropriate locations in the IC floor plan, and route the interconnections between the various cells to generate an IC layout. After a layout is generated, a series of verification and acceptance procedures are performed, including design rule checks (DRC) and layout versus schematic (LVS) checks. When a design has passed its verification procedures, signoff and tapeout occur. The layout is released to a foundry using a standard format, such as GDSII or Oasis.
An IC designer designs circuits using the standard cell libraries that are available at the time a given IC is designed. After the initial release of a given IC, foundries and cell library vendors continue to enhance their cell libraries with new cell designs. It would be costly for IC designers to redesign their ICs to take advantage of later developed cell designs.